Fabrication of recordable electrical memory

ABSTRACT

A memory cell of a memory device is fabricated by forming a first electrode on a substrate, positioning a photo mask at a first position relative to the substrate, and forming a first material layer on the first electrode based on a pattern on the photo mask. The photo mask is positioned at a second position relative to the substrate, and a second material layer is formed above the first material layer based on the pattern on the photo mask, the second material layer being offset from the first material layer so that a first sub-cell of the memory cell includes the first material layer and not the second material layer, and a second sub-cell of the memory cell includes both the first and second material layers. A second electrode is formed above the first and second material layers.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of U.S. Provisional Application Ser.No. 60/917,740, filed May 14, 2007. This application is related to U.S.patent application Ser. No. 11/855,532, titled “Recordable ElectricalMemory”, filed on Sep. 14, 2007, and U.S. patent application Ser. No.11/855,537, titled “Recordable Electrical Memory”, filed on Sep. 14,2007. The contents of the above applications are incorporated herein byreference.

BACKGROUND

This invention relates to fabrication of recordable electrical memory.

Non-volatile memory (NVM) has found its usage in several majorapplication areas, such as program storage for microcontroller units(MCU), read only memory (ROM), multimedia content storage, and Flashmemory cards. Both ROM and Flash memory include an array of addressablememory cells. Word lines and bit lines define the address of each cell.In Flash memory devices, each cell includes a floating gate metal oxidesemiconductor (MOS) transistor, in which an electrically isolatedfloating gate is used to store charges. Flash memory devices havedifferent types of architectures, such as NOR flash or NAND flash, thatare suitable for different applications. Another example of anon-volatile memory device uses an electrically writeable and erasablephase change material that can be switched between generally amorphousand generally crystalline states.

SUMMARY

In a general aspect, information is recorded in a non-volatileelectrical memory through a change of one or more material properties ofa recordable layer. The recordable layer may include one or more thinlayers of materials. Electrical circuitry, such as electricalconductors, are arranged such that at different locations of the layerthe circuitry can (1) perform inscription by introducing a currentthrough the layer thereby changing material and electrical properties atthat location and/or (2) perform reading by sensing the electricalproperties, such as resistance, at that location.

In another general aspect, information is recorded in a non-volatileelectrical memory by generating contrast between different states ofmemory cells, the states including an initialized state and one or moreinscribed states. Information is read from each of the memory cells bycomparing a value read from the memory cell to one or more preset valuesand determining whether the memory cell is in the initial state or oneof the inscribed states. For example, the value can be a resistancevalue.

In another general aspect, information is recorded in a non-volatileelectrical memory by generating contrast in resistance using one or morethin layers of organic and/or inorganic material.

In another general aspect, a method for fabricating a memory cell of amemory device includes forming a first electrode on a substrate,positioning a photo mask at a first position relative to the substrate,and forming a first material layer on the first electrode based on apattern on the photo mask. The photo mask is positioned at a secondposition relative to the substrate, and a second material layer isformed above the first material layer based on the pattern on the photomask, the second material layer being offset from the first materiallayer so that a first sub-cell of the memory cell includes the firstmaterial layer and not the second material layer, and a second sub-cellof the memory cell includes both the first and second material layers. Asecond electrode is formed above the first and second material layers.

Implementations of the method can have one or more of the followingfeatures. The method includes positioning the photo mask at a thirdposition and forming a third material layer above the first and secondmaterial layers based on the pattern on the photo mask, the thirdmaterial layer being between the first electrode and the secondelectrode, the third material layer being offset from the first andsecond material layers so that the memory cell includes at least thefirst sub-cell, the second sub-cell, and a third sub-cell. The firstsub-cell includes the first material and not the second or thirdmaterial layers, whereas the second sub-cell includes the first andsecond material layers and not the third material layer. The thirdsub-cell includes the first and third material layers and not the secondmaterial layer. The memory cell includes a fourth sub-cell that includesthe first, second, and third material layers. The distance between thefirst position and the second position is less than a smallest linewidth of the photo mask.

In some examples, the method includes positioning the photo mask at afourth position and forming a fourth material layer above the first,second, and third material layers based on the pattern on the photomask, the fourth layer being between the first electrode and the secondelectrode, the fourth material layer being offset from the first,second, and third material layers so that the memory cell comprises atleast the first sub-cell, the second sub-cell, the third sub-cell, and afourth sub-cell. In some examples, the method includes positioning thephoto mask at a fifth position and forming a fifth material layer abovethe first, second, third, and fourth material layers based on thepattern on the photo mask, the fifth material layer being offset fromthe first, second, third, and fourth material layers so that the memorycell comprises at least the first sub-cell, the second sub-cell, thethird sub-cell, the fourth sub-cell, and a fifth sub-cell.

Positioning the photo mask at the second position includes shifting thephoto mask for a distance from the first position to the second positionin which the distance is less than a smallest line width of the photomask. Forming the first layer includes forming a layer of materialhaving openings, the openings to allow portions of the first electrodeto electrically contact portions of the second electrode. Forming thefirst material layer includes forming a semiconductor layer or adielectric layer. The method includes forming circuitry for applying awrite signal to the memory cell. The method includes forming circuitryfor outputting a read signal from the memory cell.

In another general aspect, a method includes fabricating sub-cells of amemory cell by positioning a photo mask at different positions anddepositing material layers based on the photo mask at each of thedifferent positions, different sub-cells having different materiallayers or different combinations of material layers.

In another general aspect, a method includes fabricating a memory devicehaving memory cells, each memory cell having at least two sub-cells,including positioning a photo mask at two or more positions, the photomask having a predetermined pattern, and for each position of the photomask, forming at least one material layer based on the predeterminedpattern of the photo mask to cause different sub-cells to have differentmaterial layers or different combinations of material layers.

Implementations of the method can have one or more of the followingfeatures. Fabricating the sub-cells includes positioning the photo maskat three positions to form four sub-cells. Fabricating the sub-cellsincludes positioning the photo mask at five positions to form ninesub-cells. In some examples, fabricating the sub-cells includesdepositing a first layer on a lower electrode, adjusting an alignment ofthe photo mask, and depositing a second layer on the first layer. Afirst sub-cell includes the first layer and not the second layer, and asecond sub-cell includes both the first and second layers. In someexamples, fabricating the sub-cells includes depositing a first layer ona lower electrode, etching the first layer, adjusting an alignment ofthe photo mask, depositing a second layer on the first layer and anexposed portion of the lower electrode, and etching the second layer. Afirst sub-cell includes the second layer and not the first layer, and asecond sub-cell includes both the first and second layers.

Each material layer has a portion that overlaps a portion of anothermaterial layer. Positioning the photo mask at two or more positionsincludes positioning the photo mask a first position and a secondposition spaced apart from the first position by a distance that is lessthan a smallest line width of the photo mask. Forming at least onematerial layer for each position of the photo mask includes forming alayer of material having openings, the openings allowing portions of thefirst electrode to electrically contact portions of the secondelectrode. Forming at least one material layer includes forming at leastone semiconductor or dielectric layer.

In another general aspect, a method includes fabricating an electronicdevice on a substrate using a photolithography process. Boundaries ofcomponents of the electronic device are defined by positioning a photomask at a position relative to the substrate, and shifting an alignmentof the photo mask according to a sequence of steps when definingboundaries of different components, in which the smallest distance ofshift during the sequence of steps is smaller than a smallest line widthof the electronic device.

Implementations of the method can have one or more of the followingfeatures. The electronic device can include a memory device having aplurality of memory cells. Each memory cell can include two or moresub-cells. The method includes forming layers of materials as the photomask is shifted according to the sequence of steps to form materiallayers that are offset from one another to form components havingdifferent layers or different combinations of layers.

In another general aspect, a lithography system includes a wafer stageto support a wafer, a photo mask stage to support a photo mask, at leastone stepper motor to drive the photo mask stage, and a programmablecontroller to control the at least one stepper motor to move the photomask stage according to a sequence of steps to fabricate sub-cells ofmemory cells on the wafer, each of some of the steps involving amovement of the photo mask stage for a distance less than the smallestline width of the photo mask such that the sub-cells have dimensionssmaller than the smallest line width of the photo mask. A storage storesinstructions that when executed cause the programmable controller tocontrol the at least one stepper motor to move the photo mask stageaccording to the sequence of steps to fabricate memory cells each havinga plurality of sub-cells.

Implementations of the system can have one or more of the followingfeatures. The instructions when executed cause the programmablecontroller to control the at least one stepper motor to move the photomask stage to position the photo mask at various locations to cause afirst material layer to be formed at a position that is offset adistance relative to a position of a second material layer, forming afirst sub-cell that includes the first material layer but not the secondmaterial layer, and a second sub-cell that includes both the first andsecond material layers, the offset distance being less than the smallestline width of the photo mask.

In another general aspect, an apparatus includes means for definingboundaries of sub-cells of memory cells of a memory device bypositioning a photo mask at a position relative to a substrate on whichthe memory device is fabricated, and means for shifting alignment of thephoto mask according to a sequence of steps in which the smallestdistance of shift during the sequence of steps is smaller than asmallest width of the memory cell.

In another general aspect, a memory device includes memory cells eachincluding a recordable layer between two metal layers. Each memory cellis constructed and designed to change from a first state to a secondstate upon application of an initialization signal, and change from thesecond state to a third state upon application of a write signal. For avoltage within a specified range that is applied across the two metallayers, the memory cell has a lower resistance in the first state thanin the second state, and has a higher resistance in the second statethan in the third state.

Implementations of the memory device can have one or more of thefollowing features. Substantially all of the memory cells areinitialized by applying the initialization signal to the memory cells tocause the memory cells to enter the second state. Information isrecorded in the memory cells based on contrasts of the second state andthe third state in the memory cells. In the first state, the memory cellhas a resistor-like current-voltage characteristic for voltages within apredetermined range. In the second state, the memory cell has adiode-like current-voltage characteristic. In the third state, thememory cell has a resistor-like current-voltage characteristic forvoltages within a predetermined range. The memory cell has a lowerresistance in the third state than in the first state. The recordablelayer includes at least one of a semiconductor or a dielectric material,e.g., silicon, germanium, SiGe, SiC, or diamond. The recordable layerhas a thickness less than 50 nm. The specified range is from −1V to 1V.The initialization signal includes a pulse having a voltage less than3V. The write signal includes a pulse having a voltage greater than 2V.In the first state, the recordable layer has openings that allowportions of the first metal layer to contact the second metal layer.Upon application of the initialization signal, the portions of the firstmetal layer that contact the second metal layer form an alloy with thematerial of the recordable layer. In the second state, a Schottky-likebarrier is formed between the alloy and at least one of the first andsecond metal layers. The first and second metal layers include at leastone of aluminum, gold, silver, titanium, copper, and aluminum alloys.The memory device includes circuitry for outputting a signal indicatingwhether a selected one of the memory cells is in the second state or thethird state.

In another general aspect, a memory device includes a plurality ofmemory cells each including a recordable layer between two metal layers.Each memory cell is constructed and designed to change from anas-deposited state to an initialized state upon application of aninitialization signal, and change from the initialized state to aninscribed state upon application of a write signal. The memory cell hasa resistor-like current-voltage (I-V) characteristic when in theas-deposited state, a diode-like I-V characteristic when in theinitialized state, and a resistor-like I-V characteristic when in theinscribed state for voltages within a predetermined range.

Implementations of the memory device can have one or more of thefollowing features. When a read signal having a voltage between −1.8V to1.8V is applied across the two metal layers to measure the resistance ofa memory cell, the memory cell has a lower resistance in theas-deposited state than in the initialized state, and has a higherresistance in the initialized state than in the inscribed state. Theinitialization signal has a voltage level between two times a voltagelevel of a read signal and 75% of a voltage level of the write signal.When the memory cell is in the inscribed state, the memory cell has aresistor-like I-V characteristic for voltages below a firstpredetermined value, and has a diode-like I-V characteristic forvoltages above a second predetermined value. Information is recorded inthe memory cells based on contrasts of the initialized state and theinscribed state in the memory cells. A resistance of the memory cellrelative to a reference value is indicative of information recorded inthe memory cell.

In another general aspect, a memory device includes a plurality ofmemory cells each including a recordable layer between two metal layers,the recordable layer including a material different from that of the twometal layers, the recordable layer defining openings that allow portionsof the first metal layer to contact the second metal layer, therecordable layer having a thickness less than 50 nm.

Implementations of the memory device can have one or more of thefollowing features. Each memory cell is constructed and designed tochange from a first state to a second state upon application of aninitialization signal, and change from the second state to a third stateor from the second state to a fourth state upon application of a firstwrite signal or a second write signal, respectively. In the first state,the memory cell has a resistor-like current-voltage characteristic forvoltages within a predetermined range. In the second state, the memorycell has a diode-like current-voltage characteristic. In the third andfourth states, the memory cell has resistor-like current-voltagecharacteristics for voltages within a predetermined range. The memorycell has a lower resistance in the first state than in the second state.The recordable layer includes at least one of a semiconductor or adielectric material. The recordable layer includes islands of amaterial.

In another general aspect, a method includes initializing memory cellsof a memory device by applying an initialization signal to each of thememory cells to cause the memory cell to change from an as-depositedstate to an initialized state, the memory cells in the initialized statebeing capable of changing to an inscribed state upon receiving a writesignal. Each of the memory cells has a resistor-like current-voltage(I-V) characteristic when in the as-deposited state, a diode-like I-Vcharacteristic when in the initialized state, and a resistor-like I-Vcharacteristic when in the inscribed state for voltages within apredetermined range.

Implementations of the method can have one or more of the followingfeatures. The method includes applying the write signal to some of thememory cells to cause the memory cells to change to the inscribed state.

In another general aspect, a method includes initializing memory cellsof a memory device by applying an initialization signal to each of thememory cells to cause the memory cell to change from a first state to asecond state, the memory cells in the second state being capable ofchanging to a third state upon receiving a write signal. For a voltagewithin a specified range that is applied to the memory cell, the memorycell has a lower resistance in the first state than in the second state,and has a higher resistance in the second state than in the third state.

Implementations of the method can have one or more of the followingfeatures. The method includes recording information in the memory cellsby generating contrasts between the second and third states in thememory cells. In the first state, each of the memory cells includes arecordable layer positioned between a first metal layer and a secondmetal layer, and the recordable layer has openings that allow portionsof the first metal layer to contact the second metal layer. Initializingthe memory cell includes causing the portions of the first metal layerthat contact the second metal layer to form an alloy with the materialin the recordable layer. The method includes testing whether each memorycell is functional. Testing whether the memory cell is functionalincludes determining whether the memory cell has a resistance higherthan a specified value in the first state, and determining whether thememory cell has a resistance higher than a specified value in the secondstate.

In another general aspect, a method of fabricating a memory deviceincludes depositing a layer of semiconductor or dielectric material on afirst metal layer, the layer of semiconductor or dielectric materialhaving a thickness less than 50 nm and having openings that expose thefirst metal layer, and depositing a second metal layer on the layer ofsemiconductor or dielectric material, a portion of the second metallayer contacting the first metal layer through the openings in the layerof semiconductor or dielectric material.

Implementations of the method can have one or more of the followingfeatures. The method includes forming words lines and bit lines forselecting one of a plurality of memory cells each includes acorresponding different portion of the first metal layer, the secondmetal layer, and the layer of semiconductor or dielectric material. Themethod includes initializing the memory cells by applying aninitialization signal to each of the memory cells to cause the memorycell to change from a first state to a second state, the memory cells inthe second state being capable of changing to a third state uponreceiving a write signal.

In another general aspect, a memory device includes a plurality ofmemory cells each including a recordable layer between two metal layers,the recordable layer including a first sub-cell and a second sub-cell.Each memory cell is constructed and designed to change from anas-deposited state to an initialized state upon application of aninitialization signal, from the initialized state to a first inscribedstate upon application of a first write signal, and from the initializedstate to a second inscribed state upon application of a second writesignal. The memory cell has a resistor-like current-voltage (I-V)characteristic when in the as-deposited state, a diode-like I-Vcharacteristic when in the initialized state, and resistor-like I-Vcharacteristics when in the first and second inscribed states forvoltages within a predetermined range.

Implementations of the memory device can have one or more of thefollowing features. The first sub-cell has a thickness that is differentfrom the thickness of the second sub-cell. The first sub-cell has afirst number of layer(s) of material(s) that is different from a secondnumber of layer(s) of material(s) in the second sub-cell. The firstsub-cell includes a material that is different from a material in thesecond sub-cell. The first sub-cell has a morphology that is differentfrom the morphology of the second sub-cell. The recordable layerincludes at least one of a semiconductor or a dielectric material. For avoltage within a specified range that is applied across the two metallayers, the memory cell has a lower resistance in the as-deposited statethan in the initialized state, a higher resistance in the initializedstate than in the first inscribed state, and a higher resistance in theinitialized state than in the second inscribed state.

In another general aspect, a memory device includes memory cells eachincluding a recordable layer between two metal layers, the recordablelayer includes at least a first sub-cell and a second sub-cell, in whicheach memory cell is constructed and designed to change from a firststate to a second state upon application of an initialization signal,and from the second state to a third state or from the second state to afourth state upon application of a first write signal or a second writesignal, respectively. For a voltage within a specified range that isapplied across the two metal layers, the memory cell has a lowerresistance in the first state than in the second state, a higherresistance in the second state than in the third state, and a higherresistance in the second state than in the fourth state.

Implementations of the memory device can have one or more of thefollowing features. The first sub-cell has a thickness that is differentfrom the thickness of the second sub-cell. The first sub-cell has afirst number of layer(s) of material(s) that is different from a secondnumber of layer(s) of material(s) in the second sub-cell. The firstsub-cell includes a material that is different from another material inthe second sub-cell. The first sub-cell and second sub-cells havedifferent morphologies. The recordable layer includes at least one of asemiconductor or a dielectric material. Substantially all of the memorycells are initialized by applying the initialization signal to thememory cells to cause the memory cells to enter the second state. Thefirst sub-cell is configured to be activated by the first write signal,and the second sub-cell is configured not to be activated by the firstwrite signal. The first and second sub-cells are configured to beactivated by the second write signal.

Ternary information is recorded in the memory cells based on contrastsbetween the second state, the third state, and the fourth state in thememory cells. Each memory cell is constructed and designed to changefrom the second state to a fifth state upon application of a third writesignal. Quaternary information is recorded in the memory cells based oncontrasts between the second state, the third state, the fourth state,and the fifth state in the memory cells. Each memory cell is constructedand designed to change from the second state to an i-th state uponapplication of a j-th write signal, i being any number from 5 to n+1,wherein n≧5 and j=i−2. N-nary information is recorded in the memorycells based on contrasts between the second to (n+1)-th states in thememory cells.

A resistance of a memory cell relative to reference values is indicativeof information recorded in the memory cell. In the first state, thememory cell has a resistor-like current-voltage characteristic forvoltages within a predetermined range. In the second state, the memorycell has a diode-like current-voltage characteristic. In the third andfourth states, the memory cell has resistor-like current-voltagecharacteristics for voltages within a predetermined range. The memorycell has a lower resistance in the third state than in the first state.The memory cell has a lower resistance in the fourth state than in thethird state. The recordable layer has a thickness less than 50 nm. Thespecified range is from −1V to 1V. The initialization signal includes apulse having a voltage less than 3V. The first and second write signalseach includes a pulse having a voltage greater than 2V.

In the first state, at least one of the first and second sub-cellsdefines openings that allow portions of the first metal layer toelectrically contact the second metal layer. Upon application of theinitialization signal, portions of the first metal layer form an alloywith the material of the recordable layer. In the second state, aSchottky-like barrier is formed between the alloy and at least one ofthe first and second metal layers. The first and second metal layersinclude at least one of aluminum, gold, silver, titanium, copper, andaluminum alloys. The layer of semiconductor or dielectric materialincludes at least one of silicon, germanium, SiGe, SiC, and diamond. Thememory device includes circuitry for outputting a signal indicatingwhether the memory cell is in the second state, the third state, or thefourth state.

In another general aspect, a memory device includes a plurality ofmemory cells each including a recordable layer positioned between twometal layers, the recordable layer including at least a first sub-celland a second sub-cell, at least one of the sub-cells having openingsthat allow portions of the first metal layer to electrically contact thesecond metal layer, the recordable layer having a thickness less than 50nm.

Implementations of the memory device can have one or more of thefollowing features. Each memory cell is constructed and designed tochange from a first state to a second state upon application of aninitialization signal, change from the second state to a third stateupon application of a first write signal, and change from the secondstate to a fourth state upon application of a second write signal,respectively. In the first state, the memory cell has a resistor-likecurrent-voltage characteristic for voltages within a predeterminedrange. In the second state, the memory cell has a diode-likecurrent-voltage characteristic. In the third and fourth states, thememory cell has resistor-like current-voltage characteristics forvoltages within a predetermined range. The first sub-cell is configuredto be activated by the first write signal, and the second sub-cell isconfigured not to be activated by the first write signal. The first andsecond sub-cells are configured to be activated by the second writesignal.

In another general aspect, a method includes initializing memory cellsof a memory device by applying an initialization signal to each of thememory cells to cause the memory cell to change from a first state to asecond state, the memory cells in the second state being capable ofchanging to a third state upon receiving a first write signal, thememory cells in the second state being capable of changing to a fourthstate upon receiving a second write signal. For a voltage within aspecified range that is applied to the memory cell, the memory cell hasa lower resistance in the first state than in the second state, has ahigher resistance in the second state than in the third state, and has ahigher resistance in the second state than in the fourth state.

Implementations of the method can have one or more of the followingfeatures. The method includes recording ternary information in thememory cells by generating contrasts between the second state, the thirdstate, and the fourth state in the memory cells. The method includesactivating the first sub-cell but not the second sub-cell by applyingthe first write signal. The method includes activating the secondsub-cell by applying the second write signal. In the first state, thememory cell includes a recordable layer between a first metal layer anda second metal layer, the recordable layer has a first sub-cell and asecond sub-cell, and at least one of the sub-cells has openings thatallow portions of the first metal layer to electrically contact thesecond metal layer. Initializing the memory cell includes causingportions of the first metal layer to form an alloy with the material inthe recordable layer. The method includes testing whether each memorycell is functional. Testing whether the memory cell is functionalincludes determining whether the memory cell has a resistance lower thana specified value in the first state, and determining whether the memorycell has a resistance higher than a specified value in the second state.

Aspects can have one or more of the following advantages. The recordableelectric memory devices can be cost-effective (i.e., low cost-per-bit),user friendly, field programmable, require short lead time, and cansatisfy a wide variety of applications, such as MP3 players, cellularphones, personal digital assistants, digital cameras, and camcorders,etc. The memory cells can be initialized to a stable state havingpredefined characteristics, so that it is easy to detect defectivememory cells and avoid the use of the defective cells. A memory cell canhave more than one inscribed state, so that multi-nary data can bestored in the memory cells. Each memory cell can have n sub-cells, inwhich the n sub-cells can be fabricated using the same photolithographymask by using a mask shifting technique. The n sub-cells can befabricated using less than n alignment adjustment steps. Only a smallamount of power is needed to write data to the recordable electricalmemory device. The recordable electrical memory device can have a highdensity of memory cells, hence a higher storage capacity than many othertypes of memory devices (including flash memory) of the same physicalsize. Fabrication of the recordable electrical memory device uses lessmaterial, and also can use a simpler fabrication process, as compared toflash memory. The recordable electric memory can be fabricated usingstate of the art CMOS manufacturing process. Data is written in therecordable electrical memory device based on material change, and so thedata will be less susceptible to electrical magnetic interference.

Other features and advantages of the invention will be apparent from thefollowing description, and from the claims.

DESCRIPTION OF DRAWINGS

FIGS. 1A to 1C show a perspective view, a side view, and a top view,respectively, of a portion of a recordable electrical memory device.

FIGS. 2A to 2C are diagrams of a memory cell including a recordablelayer that has openings or islands of a material.

FIG. 3 show I-V curves of a memory cell that has one inscribed state.

FIG. 4 shows I-V curves of a memory cell that has four inscribed states.

FIGS. 5A to 5E show a process of fabricating a memory cell having fourdistinct inscribed states by using photolithography alignmentadjustment.

FIGS. 6A to 6C are diagrams of equivalent circuits of memory cells.

FIGS. 7A to 7F show a process for fabricating a memory cell having ninedistinct inscribed states using photolithography alignment adjustment.

FIG. 8 shows a process for fabricating a memory cell that can storequaternary information.

FIG. 9 shows a chip that includes a recordable electrical memory areafor fabricating a recordable electrical memory device.

FIG. 10 is a cross sectional diagram of a portion of a recordableelectrical memory area and a portion of a chip area outside of therecordable electrical memory area.

FIGS. 11A to 11F show top views of layers of an NOR type recordableelectrical memory device.

FIG. 12 is a block diagram of a memory device that includes a memorycontroller and multiple memory arrays.

FIG. 13 is a block diagram of a memory controller.

FIG. 14 is a block diagram of a micro-controller unit that includes arecordable electrical memory device 100.

FIG. 15 is a schematic diagram representing recordable electrical memorydevices.

FIGS. 16A and 16B are graphs that show experimental data for a sample ofa recordable electric memory that was configured to have one inscribedstate.

FIGS. 17A and 17B are graphs that show experimental data for samples ofrecordable electrical memory devices that are configured to have threeinscribed states.

FIG. 18 is a schematic diagram of a cross section of a dual-layerrecordable electrical memory device.

DETAILED DESCRIPTION

1. Overview

FIGS. 1A, 1B, and 1C show a perspective view, a side view, and a topview, respectively, of a portion of a recordable electrical memorydevice 100. The memory device 100 includes a recordable layer 110. Amaterial property of the layer is modified upon application of anenergy, thereby “writing” a mark to the layer. A material property ofthe layer (such as electrical resistance, resistivity) can be laterdetected using electrical methods (such as by applying an electricalread signal). Information is recorded in the memory device 100 based oncontrast in the material property with respect to one or more referencevalues that can be detected, thereby “reading” from the layer todetermine if a mark was previously written. For example, the resistanceof a cell can be compared with one or more reference values to determinewhether information is recorded in the region. The reference values canbe, e.g., resistance values of reference cells. By using accesscircuitry that allows selective access to individual locations of therecordable layer 110, the memory device 100 can have multiple memorylocations that can be individually modified and detected (i.e., writtenand read).

In this description, a change in a material property of a layer includeschanges to the type(s), density (or densities), or arrangement(s) ofatoms or molecules in the layer. A change in material property of alayer may be associated with a change in one or more electricalproperties (such as resistivity and junction characteristics, such as aSchottky barrier or an ohmic junction) of the layer. A change inmaterial property does not mean a change merely in the amount ofelectric charges accumulated at particular locations, such asaccumulating charges in a capacitor or a floating gate.

In some examples, the access circuitry includes word lines 140 that arepositioned on one side 116 of the recordable layer 110 and extend alongan x-direction. Parallel word lines 140 are spaced apart along ay-direction. Bit lines 130 are positioned on another side 118 of therecordable layer 110 and extend along the y-direction. Parallel bitlines 130 are spaced apart along the x-direction. At each intersectionof a word line 140 and a bit line 130 is a memory cell 120 that can beindividually addressed. Information is recorded in the memory cell 120by applying a write signal through a selected pair of a word line and abit line, thereby changing a material property of a portion of therecordable layer 110 at the memory cell 120.

The word lines 140 and the bit lines 130 do not necessarily contact thememory cells 120 directly. The lines 130 and 140 may be electricallyconnected to the memory cells 120 through conducting layers orconducting lines.

The memory cells 120 do not necessarily have distinct boundaries. Insome examples of the recordable electrical memory device 100, therecordable layer 110 may include one or more continuous layers ofmaterials, so the term “memory cell” is used in general to include aportion of the recordable layer 110 that can be individually accessed,such as by a selected pair of word and bit lines.

A memory cell 120 may include electrodes that are connected to the wordand bit lines, and may include other components. A memory cell can haveone or more sub-cells. Each sub-cell can have one or more sub-layers,and different sub-cells can have different sub-layers or differentcombinations of sub-layers.

In some examples, the recordable layer 110 spans several memory cells120, and conductive word and bit lines are electrically connected to therecordable layer 110. As described below, the recordable layer 110 canhave an unwritten (“virgin” or “as-deposited”), an initialized state,and an inscribed state. The electrical property of the recordable layer110 has characteristics such that (1) in the unwritten state, themajority of electric current can only pass through the memory celldefined by the word and bit lines, (2) the electric current that passesthrough the defined memory cell is small compared to any of theinscription states (this can be achieved by choosing process parametersso that the unwritten state has a higher resistance compared to theinscription states), and (3) the initialized state can have a higherresistance than the unwritten state.

Energy can be applied to the recordable layer 110 to change theresistance (electrical properties) of a region defined by the electrodesof the selected memory cell, for example, by applying an initializationsignal or a write signal having a power level and/or duration sufficientto cause the modification in material property in the recordable layer110. The initialization signal or write signal may include a singlepulse, or a series of sub-pulses (or other suitable voltage or currentdriving signal).

As shown in FIG. 1B, when an initialization signal or a write signal isapplied to a memory cell 120, the initialization signal or write signalmay induce an electric current to flow through the memory cell 120 andgenerate thermal energy, which causes the modification of materialproperty in the recordable layer 110, for example, by causing a chemicalreaction in the cell, or causing different materials to intermix. Thematerial change may be irreversible in that other signals cannot beapplied to reverse the modification of the material property. Examplesof the material properties that may change upon application of the writesignal include resistivity and junction characteristics, such as aSchottky barrier or an ohmic junction, within the layer.

In this description, a memory cell 120 can have an as-deposited state,an initialized state, and one or more inscribed states. The term“as-deposited state” refers to a condition in which the layers of therecordable electrical memory device 100 have been deposited and beforeinitialization of the memory cell 120, so that the recordable layer 110maintains its “virgin” material and electrical properties. The term“initialized state” refers to a condition after an initialization signalhas been applied and before a write signal has been applied to thememory cell 120. The initialization signal causes a change in a materialproperty (as well as an electrical property) in the recordable layer110. The initialized state is a stable state that has electricalcharacteristics that may be different from the as-deposited state andthe inscribed state(s). The term “inscribed state” refers to a conditionafter the write signal has been applied so that another material changeoccurs in the recordable layer 110, resulting in further change in amaterial property (as well as an electrical property). The term“initialized mark” refers to a portion of the recordable layer 110 inthe initialized state, and the term “recorded mark” refers to a portionof the recordable layer 110 in the inscribed state.

2. Memory Cells

The recordable layer 110 can be composed of various materials. Dependingon the configuration for the memory cells 120, the memory cell 120 canhave, for example, (1) an as-deposited state, an initialized state, andone inscribed state, or (2) an as-deposited state, an initialized state,and multiple inscribed states. In the first case, when a memory cell 120is in the initialized state, applying a write signal causes the memorycell 120 to change to the inscribed state. Each memory cell can be usedto record binary information. In the second case, when a memory cell 120is in the initialized state, applying a write signal causes the memorycell 120 to change to one of multiple inscribed states. Each memory cellcan be used to record, e.g., ternary, quaternary, or n-nary information.

2.1 Initialization and Inscription of Memory Cells

The initialization and inscription of memory cells are described below.Memory cells 120 that have an as-deposited state, an initialized state,and one or more inscribed states can be fabricated using layers thatperform a first material change upon application of an initializationsignal, and perform additional material change(s) upon application of awrite signal.

Referring to FIG. 2A, in some examples, a memory cell 120 includes athin recordable layer 110 positioned between a first (lower) metalelectrode 152 and a second (upper) metal electrode 154. The first andsecond electrodes 152 and 154 can be made of, for example, aluminum. Therecordable layer 110 can be made of a semiconductor material, e.g.,silicon, germanium, SiGe, and SiC. The semiconductor material can beeither n-type or p-type, and can be doped with impurities. Therecordable layer 110 can also be made of a dielectric material, e.g.,diamond. The recordable layer 110 can have a thickness (or an effectivethickness), e.g., less than 100, 50, 25, 10, 5, 3, or 1 nm. The firstelectrode 152 and the second electrode 154 can be electrically connectedto, e.g., the word line 140 and the bit line 130, respectively. Thefirst and second metal electrodes 152 and 154 each can be made of, e.g.,aluminum, gold, silver, titanium, copper, or alloys of the above metals,and can have a thickness, e.g., greater than 50 nm.

In some examples, the recordable layer 110 has openings 156 to allow thefirst metal electrode 152 to contact the second metal electrode 154. Theopenings 156 have areas that are small, so that the recordable layer 110is not entirely conductive. The memory cell 100 has resistor-likecurrent-voltage (I-V) characteristics. The resistor-like current-voltagecharacteristics can include, for example, a current-voltage relationshipthat is substantially linear. The resistance of the memory cell 120 inthe as-deposited state can be, e.g., in the order of gigaohms when thememory cell has an area of 1 μm².

The recordable layer 110 can be fabricated by depositing discontinuousregions or islands 150 of one or more semiconductor or dielectricmaterials on the first metal electrode 152, as shown in FIG. 2B. Theislands of materials 150 have an “effective thickness,” which is definedas the volume of the material divided by the sum of the area covered bythe material and the area in between the material. The diameters of theislands 150 can be made smaller than the width of the word and bit lines140 and 130. For example, when 130 nm semiconductor fabrication processis used, the width of the word and bit lines can be 130 nm, and thediameter of the islands 150 can be made to be about 10 nm. Because eachword line and bit line covers several islands of materials 150, theislands 150 appear to the word and bit lines as a continuous layerhaving the effective thickness.

Islands of materials 150 can be formed by using techniques that caninclude, without limitation, physical vapor deposition, chemical vapordeposition, plasma enhanced chemical vapor deposition, metal organicchemical vapor deposition, or molecular beam epitaxy, with a lowoperating power or a short operating duration than that used for formingthe first and second metal electrodes 152, 154.

The islands 150 can have more than one type of semiconductor ordielectric material. For example, a first layer of islands of a firsttype of material is deposited, followed by deposition of a second layerof islands of a second type of material.

In some examples, the islands 150 may have different sizes, and someislands 150 may be connected. In some examples, as the material that isdeposited increases, many of the islands 150 become connected, resultingin a continuous layer of material having spaces 156 (or holes)distributed across the layer, as shown in FIG. 2C, such that the layerof material does not completely cover or overlap the other layers (e.g.,152).

The as-deposited state can be designed to have either a higherresistance or a lower resistance than at least one of the stableinscribed states. In the examples described below, it is assumed thatthe as-deposited state has a higher resistance than all the inscribedstates. For example, the memory cell 120 can be processed such that asmall sub-cell includes a recordable layer 110 having openings 156 orislands of material 150, and the contact between the first and secondelectrodes 152 and 154 is limited to the small sub-cell, so that theas-deposited state has a higher resistance than the inscribed state(s).The small sub-cell can be used for “initialization”, in which thesub-cell becomes semi-conducting after initialization, generating aSchottky barrier after initialization.

After the layer 110 of semiconductor or dielectric material is depositedon the first metal electrode 152, the second metal electrode 154 isdeposited on the recordable layer 110, filling in the spaces 156 andcontacting the first metal electrode 152. As a result of the contactsbetween the first and second metal electrodes 152, 154, the memory cells120 have resistor-like current-voltage characteristics in theas-deposited state.

After the memory device 100 has been fabricated, upon application of aninitialization signal (which can be, e.g., less than 3V), due to thermalenergy induced by the current during initialization, portions of thefirst metal electrode 152 in the openings 156 (and in some cases,portions of the second metal electrode 154 contacting the first metalelectrode 152) form an alloy with the semiconductor or dielectricmaterial in the layer 110 and become a layer of alloy material. Thematerials for the semiconductor or dielectric in layer 110, the firstmetal electrode 152, and the second metal electrode 154 are selectedsuch that a Schottky-like barrier is formed between the alloy and atleast one of the first and second metal electrodes 152, 154. As aresult, the memory cell 120 has diode-like current-voltagecharacteristics in the initialized state.

In some examples, the initialization signal can be design to be not lessthan twice the designed reading voltage and not more than 75% of thedesigned inscription voltage. For example, the initialization signal canhave a range between about 0.6 V to 2 V.

The diode-like current-voltage characteristics can include, for example,a non-linear current-voltage relationship, where the slope of thecurrent-voltage curve is small when the voltage is below a thresholdvoltage, and the slope increases significantly when the voltage islarger than the threshold voltage. Due to the Schottky-like barrier(s),the memory cell 120 does not conduct current (except for a small leakagecurrent) when a small voltage is applied to bias the memory cell 120.Current starts to flow when the forward-bias voltage increases above athreshold voltage V_(T).

As discussed above, a memory cell 120 can have a first sub-cell that hasa recordable layer 110 with openings (or islands of material), and othersub-cells having a recordable layer 110 without opening (or islands ofmaterial). The first sub-cell upon application of the initializationsignal forms an alloy so that the first sub-cell has a diode-like I-Vcharacteristics. The other sub-cells do not change upon application ofthe initialization signal.

In some implementations, a memory cell 120 can have a recordable layerhaving multiple sub-layers (for example, see FIGS. 5E, 7F, and 8). Afirst sub-cell can have one or more sub-layers with openings or islandsof material such that portions of the lower electrode electricallycontact portions of the upper electrode through the openings in therecordable layer of the first sub-cell. Other sub-cells has at least asub-layer without openings so that the lower electrode does notelectrically contact the upper electrode through the other sub-cells.Upon application of the initialization signal, the first sub-cell formsan alloy so that the first sub-cell has a diode-like I-Vcharacteristics. The other sub-cells do not change upon application ofthe initialization signal.

Upon application of a write signal (which can be, e.g., more than 2V),due to thermal energy induced by the current during application of thewrite signal, the sub-cells having a recordable layer 110 withoutopenings can react irreversibly to form an ohmic-like junction. Thesub-cell having an alloy material generated during the initializationstage can further fuse with the first and second metal electrodes 152,154 such that the interfaces between the layer 150 and the metal layers152, 154 behave similar to ohmic junctions. Thus, after application ofthe write signal, the memory cell 120 behaves like a resistor.

Because the recordable layer 110 is thin, a small amount of energy isused to record data to the memory cells 120, so data can be written intothe memory cells 120 at a fast speed. Different memory devices 100 canhave different writing pulse train strategies. In general, data can bewritten into the memory cells 120 using a writing signal having avoltage, e.g., less than 3.5 V within a few micro-seconds.

2.2 Initialize Memory Cells That Have One Inscribed State

FIG. 3 shows I-V curves of an example of a memory cell 120 that has oneinscribed state. I-V curves 160, 162, and 164 represent the currentversus voltage characteristics of the memory cell 120 in theas-deposited state, the initialized state, and the inscribed state,respectively. The memory cell 120 changes from the initialized state tothe inscribed state upon application of a write signal that has avoltage level (or power level) above a predetermined threshold.

As indicated by the I-V curve 160, in the as-deposited state, the memorycell 120 has characteristics similar to a resistor. As indicated by theI-V curve 162, in the initialized state, the memory cell 120 hascharacteristics similar to a diode. When the forward bias voltage V isless than the threshold voltage V_(T), the current I is negligible, orequal to a small leakage current that does not increase proportionallywith respect to the applied voltage V. As indicated by the I-V curve164, after application of a write signal, the memory cell 120 behaveslike a resistor, in which the current is proportional to the appliedvoltage V, even for small voltages. In this example, the resistance ofthe memory cell 120 in the inscribed state is higher than the resistanceof the memory cell in the as-deposited state.

By applying a read signal having a voltage V between 0 volt and V_(T) tothe memory cell 120, and sensing the current I that flows through thememory cell 120, one can determine whether the memory cell 120 has beeninitialized or inscribed. For example, a memory cell in the initializedstate and the inscribed state may represent a data bit of “0” and “1,”respectively.

The write signal may have a voltage level of, for example, 2 volts orhigher, and the read signal may have a voltage level of, for example,less than 1V, such as 50 to 700 mV. Information can be carried in thememory device 100 by generating contrasts in the currents amongdifferent states of the memory cells 120. In some examples, the amountof contrast in the currents between the as-deposited state and theinitialized state can be greater than 10, i.e., I1/I2≧10, where I1represents the current in the as-deposited state and I2 represents thecurrent in the initialized state for a given voltage.

When designing the memory cell 120, the type(s) of semiconductor ordielectric material(s) used for the recordable layer 110, the dopinglevel (if doping is used) of the semiconductor material, and the type(s)of metal used for the electrodes 152 and 154 are selected such that thememory cell 120 has a particular resistor-like characteristic in theas-deposited state, a particular diode-like characteristic in theinitialized state, and a particular resistor-like characteristic in theinscribed state, thereby producing a desired contrast between theas-deposited state, the initialized state, and the inscribed state.

2.3. Memory Cells That Have Multiple Inscribed States

A memory cell 120 can be configured to have multiple inscribed states bydividing the memory cell into multiple sub-cells, different sub-cellshaving different thresholds for the write signal. When the write signalis above a first threshold, a material change occurs at a firstsub-cell. When the write signal is above a second threshold, a materialchange occurs at the first sub-cell and a second sub-cell, and so forth.The material changes at different regions or at different combinationsof regions result in measurable differences in the inscribed states.

FIG. 4 shows I-V curves of an example of a memory cell 120 that has fourinscribed states. I-V curves 170, 172, 174, 176, 178, and 180 representthe current versus voltage characteristics of the memory cell 120 in theas-deposited state, the initialized state, the first inscribed state,the second inscribed state, the third inscribed state, and the fourthinscribed state, respectively. As indicated by the I-V curve 170, in theas-deposited state, the memory cell 120 has characteristics similar to aresistor. As indicated by the I-V curve 172, in the initialized state,the memory cell 120 has characteristics similar to a diode.

The memory cell 120 can be designed to enter the first, second, third,and fourth inscribed states when the write signal has a voltage levelbetween, e.g., 2 to 2.3 V, 2.5 to 2.7 V, 2.9 to 3.2 V, and 3.3 to 3.8 V,respectively. As indicated by the I-V curves 174, 176, 178, and 180,after application of a write signal that is within a first, second,third, and fourth range, the memory cell 120 behaves like a resistorhaving a first, second, third, and fourth resistance value,respectively. In this example, the resistances of the memory cell 120 inthe inscribed states are lower than the resistance of the memory cell inthe as-deposited state.

By applying a read signal having a voltage V between 0 volt and V_(T) tothe memory cell 120, and sensing the current I that flows through thememory cell 120, one can determine whether the memory cell 120 has beeninitialized or inscribed, and which inscribed state the memory cell 120is in. For example, a memory cell in the initialized state may representa data bit of “0,” a memory cell in the first, second, third, and fourthinscribed states may represent a data bit of “1,” “2,”, “3,” and “4,”respectively.

FIGS. 5A to 5D show a process of fabricating a memory cell 120 havingfour distinct inscribed states by using the technique of aphotolithography alignment. The four sub-cells of the memory cell 120are fabricated using a single photolithography mask placed at threedifferent positions.

Referring to FIG. 5A, a photolithography mask 190 having an opening 192is positioned above a region A of the memory cell 120 (the boundary ofthe memory cell is not shown in FIGS. 5A to 5C). The mask 190 ispositioned and aligned with a reference mark 193. The mask 190 is usedto form a layer of material A defined by the opening 192 at the region Ausing a photolithography process. The layer of material A is formedabove a lower electrode, and can have islands of materials or haveopenings to allow an upper electrode to contact the lower electrodethrough the openings. The material A can be a semiconductor or adielectric.

Referring to FIG. 5B, the mask 190 is shifted in the Y directionrelative to region A so that the opening 192 is positioned above aregion B (a portion of the region B overlaps the region A). The mask 190is used to form a layer of material B defined by the opening 192 at theregion B using photolithography. A portion of the layer of material Boverlaps the layer of material A. The material B can be a semiconductoror a dielectric, can have a composition and thickness that are similaror different to the material A.

Referring to FIG. 5C, the mask 190 is shifted in the X directionrelative to region A so that the opening 192 is positioned above aregion C. A portion of the region C overlaps the regions A and B. Themask 190 is used to form a layer of material C defined by the opening192 at the region C using photolithography. A first portion of the layerof material C overlaps the layer of material A but not the layer ofmaterial B, and a second portion of the layer of material C overlapsboth layers of materials A and B. The material C can be a semiconductoror a dielectric, and can have a composition and thickness that aresimilar or different to the materials A and B.

Referring to 5D, an upper electrode is formed above the region A. Aregion 195 where the upper and lower electrodes overlap (shown in dashedlines) defines the portion of the recordable layer 110 that undergoesreaction upon application of the initialization signal or the writesignal. The memory cell 120 includes four distinct sub-cells: a firstsub-cell 194 having material A, a second sub-cell 196 having materialsA+B, a third sub-cell 198 having materials A+C, and a fourth sub-cell200 having materials A+B+C. Portions of the upper electrode contact thelower electrode through openings in the material A in the first sub-cell194. The additional materials B and C not directly between theelectrodes (i.e., outside of the dashed lines in FIG. 5D) do not havesignificant effect on the operation of the memory cell 120.

In some implementations, the distance between a first position of thephoto mask 190 for forming the layer of material A and a second positionof the photo mask 190 for forming the layer of material B is less than asmallest line width of the photo mask. For example, the photo mask 190may be designed to use with a lithography system that can resolve asmallest line width w. By shifting alignment of the photo mask 190,features of the memory cell 120 having dimensions less than w can beachieved.

FIG. 5E is a perspective view of the memory cell 120 with materiallayers A, B, and C above the lower electrode 152 (the upper electrode isnot shown).

In FIGS. 5A to 5C, only one opening 192 is shown in the mask 190. Themask 190 can also have multiple openings 192 so that multiple memorycells 120 are fabricated at the same time.

When the memory cell 120 is in the as-deposited state, because ofcontacts between the upper and lower electrodes through the openings inthe material A in the first sub-cell 194, the memory cell 120 hasresistor-like current-voltage characteristics similar to the I-V curve170 of FIG. 4. The second, third, and fourth sub-cells 196, 198, and200, which have continuous layers of semiconductor or dielectricmaterials, have significantly higher impedances than the first sub-cell194.

When an initialization signal is applied to the memory cell 120, theinitialization signal causes portions of the electrodes to form an alloywith the material A in the first sub-cell 194. The interface(s) betweenthe alloy and the lower and/or upper electrodes has a Schottky-likebarrier, causing the memory cell to have diode-like current-voltagecharacteristics, similar to the I-V curve 172 in FIG. 4. Theinitialization signal is not sufficient to cause material changes in thesecond, third, or fourth sub-cells 196, 198, and 200.

When a first write signal having a first pulse waveform (which isdifferent from the initialization signal) is applied to the memory cell120 in the initialized state, the write signal causes a further materialchange in the first sub-cell 194 so that the first sub-cell 194 hasresistor-like current-voltage characteristics. The memory cell 120enters the first inscribed state, and has resistor-like current-voltagecharacteristics similar to the I-V curve 174 of FIG. 4.

When a second write signal having a second pulse waveform is applied tothe memory cell 120 in the initialized state, the write signal causes amaterial change in one of the sub-cells (e.g., the second sub-cell 196),so that the first and second sub-cells 194 and 196 have resistor-likecurrent-voltage characteristics. The memory cell 120 enters the secondinscribed state, and has resistor-like current-voltage characteristicssimilar to the I-V curve 176 of FIG. 4.

An equivalent circuit of the memory cell 120 in the second inscribedstate is shown in FIG. 6A. The first and second sub-cells 194 and 196are connected in parallel, and are represented by resistors R_(A) andR_(A+B), respectively, that are connected in parallel. The resistance ofthe memory cell 120 in the second inscribed state is less than theresistance of the cell in the first inscribed state.

When a write signal having a third pulse waveform is applied to thememory cell 120 in the initialized state, the write signal causesmaterial changes in, e.g., the second and third sub-cells 196 and 198 sothat the first to third sub-cells 194 to 198 have resistor-likecurrent-voltage characteristics. The memory cell 120 enters the thirdinscribed state, and has resistor-like current-voltage characteristicssimilar to the I-V curve 178 of FIG. 4.

An equivalent circuit of the memory cell 120 in the third inscribedstate is shown in FIG. 6B. The first, second, and third sub-cells 194,196, and 198 are represented by resistors R_(A), R_(A+B), and R_(A+C),respectively, that are connected in parallel.

When a write signal having a fourth pulse waveform is applied to thememory cell 120 in the initialized state, the write signal causesmaterial changes in, e.g., the second, third, and fourth sub-cells 196,198, and 200 so that the first to fourth sub-cells 194, 196, 198, and200 have resistor-like current-voltage characteristics. The memory cell120 enters the fourth inscribed state, and has resistor-likecurrent-voltage characteristics similar to the I-V curve 180 of FIG. 4.

An equivalent circuit of the memory cell 120 in the fourth inscribedstate is shown in FIG. 6C. The first, second, third, and fourthsub-cells 194, 196, 198, and 200 are represented by resistors R_(A),R_(A+B), R_(A−C), and R_(A+B+C), respectively, that are connected inparallel.

Examples of material changes of thin layers of materials are describedin co-pending U.S. patent application Ser. No. 11/503,671, titled“Electrical Thin Film Memory,” filed Aug. 14, 2006, herein incorporatedby reference. For example, when a write signal is applied to a memorycell 120, a current flows from the bit line 130 through the memory cell120 to the word line 140 (or vice versa), and the electric fieldgenerated across the memory cell 120 can induce stress, sometimescausing “material break down.” The electric current dissipates thermalenergy into the recordable layer 110 that is proportional to I²R, whereI represents the electric current and R represents the resistance of thememory cell 120. The thermal energy causes the recordable layer 110 toirreversibly change from the as-deposited state to the initializedstate, or from the initialized state to one of the inscribed states.

FIGS. 7A to 7F show a process of fabricating a memory cell 121 havingnine distinct inscribed states by using the photolithography alignmentadjustment technique. The nine sub-cells of the memory cell 121 arefabricated using a single photolithography mask 190 placed at fivedifferent positions. The photomask 190 has an opening 192, similar tothe photomask used in FIGS. 5A to 5D. In FIGS. 7A to 7F, the boundary ofthe opening 192 is shown, and the photomask 190 is not shown.

Referring to FIG. 7A, a layer of material A is formed above a lowerelectrode at a region A. The layer of material A can have islands ofmaterials with spacing between the islands or have openings to allow anupper electrode to contact the lower electrode. The material A can be asemiconductor or a dielectric.

Referring to FIGS. 7B to 7E, the photolithography alignment is shiftedsequentially to regions B, C, D, and E to form layers of materials B, C,D, and E. Each of the layers of materials B, C, D, and E can be asemiconductor or a dielectric, and can have a composition and thicknessthat are similar or different from the other layers. As shown in FIG.7B, a portion of the layer of material B overlaps a portion of the layerof material A. As shown in FIG. 7C, portions of the layer of material Coverlap portions of one or both layers of materials A and B. As shown inFIG. 7D, portions of the layer of material D overlap portions of one orboth layers of materials A and C. As shown in FIG. 7E, portions of thelayer of material E overlap portions of one or more of layers ofmaterials A, B, and D.

Referring to 7F, an upper electrode is formed above the region A (theentire region A is shown in FIG. 7A). A region 123 where the upper andlower electrodes overlap (shown in dashed lines) defines the portion ofthe recordable layer 110 that undergoes reaction upon application of theinitialization signal or the write signals. The region covers ninedistinct sub-cells: a first sub-cell 210 having material A, a secondsub-cell 212 having materials A+B, a third sub-cell 214 having materialsA+C, a fourth sub-cell 216 having materials A+D, a fifth sub-cell 218having materials A+E, a sixth sub-cell 220 having materials A+B+E, aseventh sub-cell 222 having materials A+B+C, an eighth sub-cell 224having materials A+C+D, and a ninth sub-cell having materials A+D+E.

The memory cell 121 of FIG. 7F having nine different sub-cells can havenine distinct inscribed states, and can store 9-nary data. Data iswritten to the memory cell 121 by using a write signal having a voltagelevel and/or pulse numbers as well as pulse durations that are selectedamong 9 different ranges or 9 different pulse waveforms.

Initialization of the memory cell 121 is similar to the initializationof the memory cell 120 (FIG. 5D). Writing data to the 9 sub-cells of thememory cell 121 is also similar to writing data to the 4 sub-cells ofthe memory cell 120, except that more write levels can be used toachieve more inscribed states.

FIG. 8 shows an example of a process 230 for fabricating a memory cell125 that can store quaternary information. A lower electrode 152 isformed on a substrate. A first layer of material is sputtered 246 ontothe lower electrode 152. A mask is positioned so that a dark pattern 237on the mask is at a first position 232 such that a portion of the firstlayer of material is masked by the dark pattern 237. An etching process248 etches away portions of the first layer of material not masked bythe dark pattern 237, resulting in a first layer of material 234remaining on the lower electrode 152. A portion (not shown in thefigure) of the first layer of material 234 that is not located betweenthe lower electrode 152 and an upper electrode does not significantlyaffect the operation of the memory cell 125.

A second layer of material 238 is formed after a second sputtering step250, a masking step 259, and a second etching step 252. The alignmentadjustment is shifted so that the dark pattern 237 is at a secondposition 236 to mask a portion of the second layer of material 238 thatis not etched. Similarly, a third layer of material 242 is formed aftera third sputtering step 254, a masking step 260, and a third etchingstep 256. A fourth layer of material 244 is formed after a fourthsputtering step 258. The fourth layer of material 244 covers the entirearea above the lower electrode 152. An upper electrode is deposited onthe fourth layer of material 244.

The memory cell 125 in FIG. 8 has four distinct sub-cells: a firstsub-cell 260 that includes the fourth layer of material 244, a secondsub-cell 262 that includes the third and fourth layers of materials 242and 244, a third sub-cell 264 that includes the second, third, andfourth layers of materials 238, 242, and 244, and a fourth sub-cell 266that includes the first, second, third, and fourth layers of materials234, 238, 242, and 244.

The fourth layer of material 244 can include islands of materials withspacing between the islands, or a layer of material having openings, sothat portions of the upper electrode contacts the lower electrodethrough the openings in the fourth layer of material 244.

2.4. Integrated Recordable Electrical Memory Device

FIG. 9 shows an example of a chip 270 that includes a RecordableElectrical MEmory (REME) area 272 for fabricating the recordableelectrical memory device 100. The device 100 includes word lines, bitlines, and the recordable layer, but does not necessarily include activedevices, such as transistors. The active devices for selecting the wordlines and bit lines are fabricated in an area 274 outside of the REMEarea 272.

The area 274 may include other circuitry, such as a central processingunit or a microcontroller. The chip 270, including the electrical thinfilm memory device 100 and other modules, can be fabricated using aprocess that is similar to the standard 1-poly, 2-metal semiconductorprocess, which is capable of fabricating devices having a poly-siliconlayer, a first metal layer, a second metal layer, and a nitride layer. Aphoto mask is used to pattern each layer to achieve the desiredgeometry.

FIG. 10 is a cross sectional diagram (not to scale) of a portion of theREME area 272 and a portion of the chip area 274 outside of the REMEarea 272. The REME area 272 includes an electrical thin-film memorydevice 100, in which a memory cell 120 is shown in the figure. Thememory cell 120 includes a portion of a recordable layer 110 thatchanges a material/electrical property after inscription.

In examples where the memory cells 120 have one inscribed state, therecordable layer 110 can be a continuous layer that covers the entirechip 270, so that it is not necessary to use an additional photo mask topattern the recordable layer 110. In examples where the memory cells 120have multiple inscribed states, the recordable layer 110 can havelocalized sub-layers. The memory cells 120 can also have one continuoussub-layer and additional localized sub-layer(s).

The recordable layer 110 is positioned between a bit line 130 (which cancontact the recordable layer 110 directly or indirectly through anelectrode, e.g., 154 in FIG. 2A) and a lower electrode 152. The bit line130 and the lower electrode are fabricated using the second metal layerand the first metal layer, respectively, of the 1-poly, 2-metal process.A word line 140 is fabricated using the poly-silicon layer of the1-poly, 2-metal process. A doped nitride region 276 provides anelectrical path from the word line 140 to the lower electrode 152.

The devices in the area 274 are also fabricated using the same 1-poly,2-metal process used for fabricating the memory cells 120. In the area274, the devices, such as transistors, can be fabricated above and/orbelow the recordable layer 110.

In some examples, the width of the bit line is 1300 nm, and thethickness of the recordable layer 110 is between about 5 nm to 50 nm.

FIG. 11A shows a top view of a layout of an NOR type recordableelectrical memory device 100 (with upper layer obscuring lower layers).The figure shows a grid reference 280 in which each small squarerepresents an area of 1λ by 1λ, λ representing the wavelength of lightused in the photolithography process to define the geometry of thelayers. Each memory cell 120 (one of which is enclosed in thick dashedlines) occupies an area of 6λ by 10λ. This size is comparable to thesize of a contact programmable NOR type ROM device. Each memory cell 120can be accessed by a bit line 130 and a word line 140. FIG. 11A showstwo complete memory cells (at the lower portion of the figure) and twopartial memory cells (at the upper portion of the figure).

Also shown in FIG. 11A are the legends for the nitride, poly-silicon,contact, metal-1, and metal-2 layers. During fabrication of the device100, in general, the nitride layer is formed first (deposited, etched,and doped), followed in sequence by the poly-silicon layer, the firstmetal layer, the recordable layer 110, and the second metal layer.

FIGS. 11B to 11F each shows the layout of a different layer of thememory device 100. FIG. 11B shows the layout of the nitride layer 276, aportion of which is doped to provide an electrical path between thepoly-silicon word line 140 and the lower electrode 152. FIG. 11C showsthe layout of the poly-silicon word lines 140. FIG. 11D shows the layoutof a lower portion 282 of the lower electrode 152. FIG. 11E shows thelayout of the lower electrode 152, which is made from the first metallayer.

FIG. 11F shows the layout of the bit lines 130, which are fabricatedfrom the second metal layer of the 1-poly, 2-metal process. Therecordable layer 110 is positioned between the bit line 130 and theupper portion of the contact 170. The recordable layer 110 is depositedon the chip 270 before the second metal layer is deposited.

When a 130 nm semiconductor fabrication process is used, each memorycell of the recordable electrical memory device 100 can have a dimensionof about 260 nm by 260 nm in the x-y plane. The reactions that occurupon application of the initialization signal and the write signal canbe endothermic reactions, so there is less heat dissipation problem,allowing multiple recordable layers to be stacked along the z-directionin a single memory device.

The photolithography process for fabricating the memory cells can beimplemented using a photolithography system having a light source, aprojection lens system, a wafer stage, a photo mask stage, steppermotors for driving the photo mask stage in the X and Y directions, and aprogrammable controller for controlling the stepper motors. The steppermotors each has a resolution smaller than the smallest width of thememory cell. In some examples, the smallest width of the memory cell isthe same as the smallest line width of the photo mask. The wafer stagesupports a substrate or wafer on which the memory devices arefabricated. The photo mask stage supports the photo mask (e.g., 190).The system includes a storage storing instructions that when executedcause the programmable controller to control the stepper motors to movethe photo mask stage according to a sequence of steps to fabricatememory cells each having a plurality of sub-cells.

For example, assume that the memory cell 120 of FIG. 5D has a dimensionof w×w, where w is the smallest line width of the photo mask 190. Thestepper motor has a resolution of w/2 so that the photo mask can beshifted a distance as small as w/2 to enable fabrication of sub-cellshaving dimensions w/2×w/2. To fabricate the memory cell 120 of FIG. 5D,the controller controls the stepper motors to shift the photo mask 190for a distance of w/2 in the +Y direction so that the opening 192 movesfrom region A to region B. The stepper motors then shift the photo mask190 in the −Y direction for a distance of w/2 and in the +X directionfor a distance of w/2 such that the opening 192 is moved to the regionC.

For example, assume that the memory cell 121 of FIG. 7F has a dimensionof w×w, where w is the smallest line width of the photo mask 190. Thestepper motor has a resolution of w/3 so that the photo mask can beshifted a distance as small as w/3 to enable fabrication of sub-cellshaving dimensions w/3×w/3. To fabricate the memory cell 121 of FIG. 7F,the controller controls the stepper motors to shift the photo mask 190for a distance of 2w/3 in the +X direction before forming the materiallayer B (FIG. 7B). The stepper motors shift the photo mask 190 for adistance of 2w/3 in the −X direction, then shift the photo mask 190 fora distance 2w/3 in the −Y direction before forming the material layer C(FIG. 7C). The stepper motors shift the photo mask for a distance of2w/3 in the +Y direction and a distance of 2w/3 in the −X directionbefore forming the material layer D (FIG. 7D). The stepper motors shiftthe photo mask for a distance of 2w/3 in the +X direction and a distanceof 2w/3 in the +Y direction before forming the material layer E (FIG.7E).

3. Theory of Thin Layers

The recordable layer 110 is thin. For example, in FIGS. 5A to 5E, thelayers of materials A, B, and C can have thicknesses 28 nm, 5 nm, and 7nm, respectively. Material properties a thin layer of material M can bedifferent from the material properties of the material M in bulk form.Without being limited by any theory presented herein, behavior ofrecordable layers having thin sub-layers may be at least partiallyunderstood according to the following. A parameter, referred to as theDebye length of a material, relates generally to the distance in thematerial to which the applied charges or fields have effect. The Debyelengths of materials of the recordable layer can be useful to predict orexplain the behavior of the recordable layer.

The combination of materials M1 and M2 during inscription may be aidedby a strong electric field created in the charges moved across theinterface between M1 and M2, and the thinness of the recording layerrelative to the Debye length of the materials in the recordable layer.That is, even without the addition of an external electric field (e.g.,between conductors), the charge transfer creates a significant electricfield.

The Debye length of a material, which relates generally to the thicknessof the cloud of charge carriers in the material that shields an appliedcharge or electric field depends on the charge carrier density. When acharged particle is placed in a material, the charged particle willattract charge carriers having opposite polarity, so that a cloud ofcharge carriers will surround the charged particle. The cloud of chargecarriers shields the electric field from the charged particle, and thehigher the charge carrier density, the greater the shielding effectwithin a given distance. Due to shielding by the charged particles, theelectric potential φ decays exponentially according the equationφ=φ₀·exp(−|x|/λ _(D)),

where φ₀ is the electric potential at the charged particle, x is thedistance from the charged particle, and λ_(D) is the Debye length, whichcan be represented by:

$\begin{matrix}{\lambda_{D} = {{\frac{1}{e}\sqrt{\frac{K \cdot T_{e}}{4\pi\; n}}} \approx {6.9\sqrt{\frac{T}{n}}\mspace{11mu}{cm}\mspace{11mu}{\left( {T\mspace{14mu}{in}\mspace{14mu}{{^\circ}K}} \right).}}}} & \left( {{Equ}.\mspace{14mu} 1} \right)\end{matrix}$See “Introduction to Plasma Physics,” by Francis Chen, Section 1.4:Debye Shielding, pages 8-11. The Debye length represents a measure ofthe shielding distance or thickness of the cloud of charge carriers.

When there are fluctuations in an electric field created by changes in alocalized charge density in a material, the influences of thefluctuations are mostly felt by charge carriers located within a fewDebye lengths. The charge density changes can be induced by, forexample, charge carriers moving through interfaces, or charge densityfluctuations induced by outside electromagnetic field or due to thermaleffects.

When two materials having different electron energy levels (such asdifferent highest unoccupied electron energy level, called conductionband, or HUMO, and lowest occupied electron energy level, called valanceband, or LOMO) contact, charge separation will cause an electric fieldto be generated at the interface. The influence of the electric field isshielded or reduced by a sheath of charge carriers near the interface.When the two materials are thin layers, for example, the total thicknessof the thin layers is less than the Debye length, there will be a strongelectric field throughout the entirety of the two layers, which can beas strong as 100,000 V/cm. The strong electric field can assist thematerials in the two layers to interact and combine upon an energyapplication (such as dissipated thermal energy induced by the writesignal). By comparison, when the layers are thick, the electric field inmost of the cross-section of the layers is negligible and does notprovide assistance in the interaction of the materials in the twolayers.

The same principle can be applied to the interaction or combination ofthree or more thin layers of materials.

For semiconductors, n (in Equ. 1) is about 10¹⁷ to 10¹⁹, its square rootis about 3×10⁸ to 3×10⁹, and T is about 300° K at room temperature, sothe Debye length is about 10 to 100 nm. For metals, n is about 10²¹ to10²³, so the Debye length is about 1 to 10 nm. For example, the Debyelength for aluminum is less than 1 nm at room temperature, and is about2 nm at 700° K. The Debye length for Ge doped with impurities is about30 nm to 80 nm at room temperature, depending on the concentration ofimpurities.

A feature of a recordable layer having thin layers is that the largeelectric field can assist endothermic reaction, which does not releaseheat during the reaction. Only a small area power density (watts/m²) isrequired to cause the combination of the two layers. The recorded markis well defined—only the portion of the two layers in which the electriccurrent passes so as to generate thermal energy above an absorbedthreshold volumetric power density, and also above an absorbed thresholdvolumetric energy density (i.e., to have enough power level and enoughduration time of high-power), will combine.

An advantage of using thin layers is that less energy may be required tocause the thin layers to combine. For a given write speed, the writesignal can have a lower voltage (for example, compared to the writingvoltage of a flash memory). For a given write signal having a specifiedvoltage, a shorter duration of the write signal can be used for writingto each memory cell, resulting in a faster writing speed. Anotheradvantage of using thin layers is that less materials for the layers arerequired, thereby reducing the material costs and the processing costsof coating or depositing the layers. When expensive materials are usedfor the layers, such as gold or silver, the cost savings formanufacturing a large number of memory devices can be significant.

When there is a strong electric field, there is an electric potentialacross the interface, so a small amount of energy can cause themolecules to move across the interface (from a higher potential regionto a lower potential region), causing a materials from the two layers tocombine. Combination of two thin layers can be achieved by, in variousversions of the system, for example, without limitation, mixing,boundary blurring, alloying, chemical reaction, diffusion, or fieldinduced mass transfer over boundary. The reaction between the two ormore layers can be endothermic or exothermic.

4. Design and Fabrication of the Memory Devices

The materials and thicknesses of the recordable layer 110 or itssub-layers can be selected based on information from a pre-establisheddatabase. The database can be established by measuring the electricalproperties of various thin layers or combinations of thin layers ofvarious materials. The database can include information about theresistance per unit area, and diode-like characteristics, of (1) asingle layer of material at different thicknesses, and (2) variouscombinations of materials of varying thicknesses, before and afterapplication of an initialization signal, and before and afterapplication of different write signals. The materials and thicknesses ofthe layers are selected to achieve a desired contrast in resistance inthe as-deposited state, the initialized state, and the inscribedstate(s).

A variety of manufacturing approaches can be used to fabricate the thinsub-layers of the recordable layer 110. For example, each layer can beformed on top of the previous layer by physical vapor deposition (PVD),chemical vapor deposition (CVD), plasma enhanced chemical vapordeposition (PECVD), metal organic chemical vapor deposition (MOCVD), ormolecular beam epitaxy (MBE).

The recordable electrical memory device 100 can be fabricated usingstandard CMOS (complementary metal oxide semiconductor) processes.Because of the simple structure of the thin film memory device 100, thememory device 100 can be fabricated using a 2-metal, 1-poly process.

5. System Architecture

FIG. 12 is a block diagram of a memory device 290 that includes the chip270, which has a memory controller 292 and multiple memory arrays 296.Each of the memory arrays 296 can be similar to the memory device 100(FIG. 1A) having memory cells 120 (FIGS. 2A, 5D, 7F, 8, and 10). Thememory controller 292 controls the memory arrays 296 through buses 294.The memory controller 292 also interacts with a host device (not shown),such as a computer or a digital camera, through an interface 298. Thememory device 290 may comply with interface standards such as UniversalSerial Bus or IEEE 1394 (Firewire) standards. The memory device 290 canbe made into a memory card, and partially comply with, for example, thecoding/decoding schemes of Compact Flash, Secure Digital, Memory Stick,or XD Memory Card standards. The memory device 290 is a write-oncedevice rather than a re-writable device. The memory device 290 does notnecessarily have to comply with the read/write voltages of the standardslisted above.

The memory controller 292 may operate in a manner compatible withexisting flash memory devices. In some examples, the memory controller292 is compatible with NOR flash architecture, and writes data to thememory arrays 296 one byte or word at a time. In some examples, thememory controller 292 is compatible with NAND flash architecture, whichread/write the data sequentially in a predefined length of memorystrings, but can randomly access which string to be read from or writtento.

Referring to FIG. 13, the memory controller 292 includes an input/outputinterface 300 that receives commands and writes data from, and outputsread data to, data pins. The commands are sent to a write controller 302that controls how data are written to or read from the memory array 296.The write controller 302 controls an address decoder 304 that receivesaddresses of the memory cells to be accessed from address pins. Theaddress decoder 304 sends row and column information to a row decoder306 and a column decoder 308, respectively, which determine which wordline and bit line to activate to access specific memory cells. A writedata buffer 314 stores data to be written to the memory array 296. Asense amplifier 310 amplifies the signals (read data) read from thememory array 296. A column multiplexer 312 multiplexes the write dataand the read data on the bit lines of the memory array 296.

For example, upon receiving an initialization command, the memorycontroller 292 may send an initialization signal having a voltage levelof, e.g., 1V, to all the memory cells 120 in the memory array 296 toinitialize the memory cells 120. Later, upon receiving a write command,the memory controller 292 may send a write signal to specified memorycells to write data in the cells. The write signal can have a voltagelevel greater than, e.g., 2V, and can have a pulse waveform thatincludes one or more pulses. The voltage level of the write signaldepends on the type of the memory cells (such as whether the memorycells are configured to store binary, ternary, quaternary data), and thedata to be written to the memory cells (such as whether to write “1,”“2,” “3,”, or “4” in a memory cell capable of storing quaternary data).Upon receiving a read command, the memory controller 292 may send a readsignal having a voltage level of, for example, 10 to 500 mV, tospecified memory cells to read data from the cells by measuring thecurrent and comparing the measured current with predetermined referencevalues.

In some examples, the memory controller 292 can translate betweenvirtual memory addresses and physical memory addresses. The host devicesends virtual memory addresses to the memory controller 292. The memorycontroller 292 translates the virtual addresses to physical addressesand accesses memory cells according to the physical addresses. Thememory device 290 may be tested at the factory for defects using aprocess described below, and the addresses of defective cells can bestored in a table. When the host device writes to the memory device 290,the memory controller 292 avoids the defective cells and only writes tofunctional memory cells.

In some examples, when the host controller sends an erase command toerase data at certain virtual addresses, the memory controller 292 maymark corresponding physical addresses as being “erased,” so that thedata at those physical addresses cannot be retrieved. When the hostdevice sends a write command to write to a virtual address that haspreviously been erased, the memory controller 292 translates the virtualaddress to a different physical address and writes to the new physicaladdress. In this way, even though the memory cells are write-once onlyand cannot be physically erased, the memory device 290 will appear tothe host device as if the memory cells can be erased for a limitednumber of times.

After the memory device 290 is fabricated and packaged, the memory cells120 of the memory array 296 can be tested according to the followingprocess.

Step 1: The gate transistor for each word line 140 is checked todetermine whether there is a defect. If the gate transistor for aparticular word line 140 is defective, the memory cells 120 using theparticular word line 140 can not be used to record data. Neitherinscription nor reading is performed to any of the memory cells 120associated with the defective word line 140 when the memory device 290is used. The world line 140 is recorded as defective in a table (whichcan be located at an area of the memory array 296 designated forrecording defects).

During testing of the device 290, information about defective word lines140 or memory cells 120 can be first stored in a memory of a host device(e.g., computer) that is testing the device 290. When the memory cells120 of the device 290 are initialized, the information about thedefective components are written to the table.

Step 2: The gate transistor of each bit (data) line 130 is checked todetermine whether there is a defect. If the gate transistor of a bitline 130 is defective, the memory cells 120 using the bit line 130cannot be used to store data. Neither inscription nor reading isperformed to any of the memory cells 120 associated with the defectivebit line 130 when the device 290 is used. The bit line 130 is recordedas defective in the table.

Step 3: Each of the memory cells 120 addressed by the two gatetransistors that passed the tests in steps 1 and 2 is checked byapplying a read signal. Each memory cell 120 should have a lowresistance value in the as-deposited state. If a particular memory cell120 has a resistance that is higher than a predetermined threshold, theparticular memory cell 120 is defective, and the address of thedefective memory cell 120 is recorded in the table.

Step 4: An initialization signal having one or a series of pulses havingpredetermined voltage level(s) is applied to each of the memory cells120 that passed the tests in steps 1 to 3. The initialization signalcauses the memory cells 120 to enter the initialized state and havediode-like current-voltage characteristics. A read signal is applied toeach of the initialized memory cell 120 to determine the resistance ofthe cell. A memory cell should have a high resistance value in theinitialized state. If a particular memory cell 120 has a resistancebelow a predetermined threshold, the memory cell 120 is marked asdefective.

After the tests in steps 1 to 4 are performed, the number of defectmemory cells 120 in the memory device 290 are counted to determinewhether the memory device 290 is suitable for sale at a certain grade orshould be discarded.

Referring to FIG. 14, the recordable electrical memory device 100 can beused as a non-volatile recordable (NVR) memory 322 of a micro-controllerunit 320. The micro-controller unit 320 also includes a centralprocessing unit 324 and a random access memory (RAM) 326. Thenon-volatile memory 322 allows the user to customize programs (e.g.,obtaining a most recent version of firmware) before permanently writingthe programs into the memory 322. During run time, the programs areloaded from the non-volatile memory 322 and stored in the RAM 326 toallow faster access of the program code. The micro-controller unit 320includes peripheral modules 328 for processing signals from input/outputports 330. The unit 320 includes a chip integration module (CIM) 334 andsupporting modules POR, LVI, and OSC. The various modules communicatewith one another through a bus 332.

Although each memory cell of the non-volatile memory 322 can beprogrammed only once, the non-volatile memory 322 can be made to have acapacity several times larger than the amount required for storing oneversion of the firmware. When the firmware needs to be upgraded, the newversion of the firmware is written to a different portion of thenon-volatile memory 322. This way, the non-volatile memory 322 can beprogrammed a finite number of times to store multiple versions of thefirmware, each time writing to a different portion of the memory 322.

6. Examples of Recordable Layers

Samples of recordable electrical memory devices were prepared and theirelectrical properties before and after initialization and inscriptionwere measured. Each recordable electrical memory device included arecordable layer having one or more thin semiconductor layers sandwichedbetween two metal electrodes. One sample of the memory device wasconfigured to store one inscribed state. Two samples of the memorydevice were configured to store four inscribed states.

FIG. 15 is a schematic diagram representing recordable electrical memorydevices 340 that were prepared. The recordable electrical memory device340 included a recordable layer 342 positioned between two layers ofmetal electrodes 344 and 346. The metal layers 344, 346 and therecordable layer 342 were deposited on a glass substrate 348. Goldcontacts 350 and 352 were deposited on the metal layers 344 and 346,respectively, to provide sufficiently large probe areas and to providegood ohmic contacts between the metal layers and the probes used tomeasure the electrical characteristics of the memory device 340.

In one sample, the memory device 340 was configured to have oneinscribed state. The recordable layer 342 included islands of materialswith spacing between the islands to allow portions of the metal layer346 to contact the metal layer 344. The recordable layer 342 was made ofp-type silicon and has a thickness of about 3 nm. The metal layers 344and 346 were made of aluminum, and each has a thickness of about 250 nm.

The recordable electrical memory 340 was fabricated using the followingprocess. Prior to depositing the thin films, the glass substrate 348 wascleaned by using a ultrasonic cleaner and was soaked in acetone orethanol for several minutes. A Modular Single Disk Sputtering System“Trio CUBE” (Balzers) equipped with two DC cathodes and one RF cathode,available from Unaxis, Balzers, Likenstain, was used to deposit thelayers. The base pressures of the main chamber and the process chamberwere maintained below 10⁻⁷ mbar. The operation pressure in the processchamber was set to be in the range of 10⁻³ to 10⁻² mbar during filmdeposition. When depositing the layers, the thicknesses of the layerswere controlled by controlling the sputtering time The thickness of eachof the thin layers was measured and estimated based on the sputteringyield of the material, the sputtering time (typically from 1 to 20seconds), and the sputtering power density (typically 4 to 15 W/cm²)used for the layer.

The sample has an overall dimension of 32×24 mm². The area between thetwo metal layers 344 and 346 was about 83 mm².

FIGS. 16A and 16B are graphs that show experimental data for the sampleof the recordable electrical memory 340 that was configured to have oneinscribed state. The data show that, for voltages between −1.8V and1.8V, the recordable electrical memory 340 has resistor-likecurrent-voltage characteristics in the as-deposited state, diode-likecurrent-voltage characteristics in the initialized state, andresistor-like current-voltage characteristics in the inscribed state.

FIG. 16A is a graph 360 that shows curves 362 and 364 representing thecurrent-voltage characteristics of the memory device 340 in theas-deposited state and the initialized state, respectively. FIG. 16B isa graph 360 that shows the curve 364 and a curve 366 that represents thecurrent-voltage characteristics of the memory device 340 in theinscribed state. The measurements were obtained for voltages between−1.8V to 1.8V.

The curve 362 indicates that, in the as-deposited state, the currentflowing through the memory device 340 is approximately linearlyproportional to the applied voltage, and the resistance is small, about2.3Ω. The curve 364 indicates that, in the initialized state, thecurrent flowing through the memory device 340 is initially small butgradually increases. When the voltage is below 1V, the current is lessthan 50 mA. When the voltage is greater than 1.7 V, the currentincreases significantly. This is similar to the current-voltagecharacteristics of a diode having a threshold voltage of about 1.7 V.

The curve 366 indicates that, in the inscribed state, the currentflowing through the memory device 340 is approximately linearlyproportional to the applied voltage, and the resistance is slightlyhigher than that in the as-deposited state. The resistance in theinscribed state is about 2.7Ω (in which the sample has an area of 83mm²).

FIGS. 17A and 17B are graphs 380 and 390, respectively, that showexperimental data for the two samples of the recordable electricalmemory device 340 that are configured to have three inscribed states.The recordable layer 342 has sub-layers A, B, and C similar to thoseshown in FIG. 5E. The sub-layers A, B, and C of the recordable layer 342is made of p-type germanium and have thicknesses of 28 nm, 5 nm, and 7nm, respectively. The data show that, for voltages between −0.5V and0.5V, the recordable electrical memory 340 has an initialized statehaving a high resistance, and three distinct inscribed states eachhaving resistor-like current-voltage characteristics. The inscribedstates have resistances that are smaller than that of the initializedstate. The differences between the two samples of FIGS. 17A and 17B mayhave been due to variations in the thicknesses of the sub-layers due todeposition equipment tolerances.

7. Alternative Recording Structures

In the examples above, generally, a recordable electrical memory devicehas one recordable layer. Alternatively, a recordable electrical memorydevice can also have two or more recordable layers, each including oneor more thin sub-layers. The additional recordable layers allow thememory device to have a larger storage capacity.

FIG. 18 is a schematic diagram of a cross section of a dual-layerrecordable electrical memory device 400 that includes a first layer 402and a second layer 404. The first layer 402 includes word lines 140 a, arecordable layer 110 a, and bit lines 130 a. The recordable layer 110 amay include one or more sub-layers and can be configured to have one ormore inscribed states. The recordable layer 110 a can be a continuouslayer that spans several memory cells, or be localized to each memorycell. A layer of insulating material 105 a fills the space between bitlines 130 a.

Similar to the first layer 402, the second layer 404 includes word lines140 b, a recordable layer 110 b, and bit lines 130 b. The recordablelayer 110 b may include one or more sub-layers and can be configured tohave one or more inscribed states. The recordable layer 110 b can be acontinuous layer that spans several memory cells, or be localized toeach memory cell. A layer of insulating material 105 b fills the spacebetween bit lines 130 b, and also serves as a buffer between the firstand second layers 402 and 404.

In some examples, the recordable layer 110 a is configured to have thesame number of inscribed states as the recordable layer 110 b. In someexamples, the recordable layer 110 a is configured to have a number ofinscribed states different from that of the recordable layer 110 b. Forexample, a first recordable layer 110 a can have a inscribed state, andthe second recordable layer 110 b can have four inscribed states. Therecordable layer 110 a may provide a faster read/write speed with alower data density because a smaller number of inscribed states allows ahigher error margin. The recordable layer 110 b may provide a slowerread/write speed with a higher data density because a larger number ofinscribed states allows a smaller error margin.

In some examples, if the memory cells in the first layer 402 and thesecond layer 404 are not accessed simultaneously, then the word line 140a of the first layer 310 a and the bit line 130 b of the second layer310 b can be combined. The same word line 140 a can be used to sendwrite and read signals to memory cells in the first layer 402 or thesecond layer 404 at different times.

Each of the first layer 402 and the second layer 404 operates in amanner similar to the memory device 100, in which the memory cells haveresistor-like I-V characteristics in the as-deposited state, diode-likeI-V characteristics in the initialized state, and resistor-like I-Vcharacteristics in the inscribed state(s).

Similar to the process for manufacturing the memory device 100, avariety of manufacturing approaches can be used to fabricate therecordable layers of the memory device 400. For example, each layer canbe formed on top of the previous layer by physical vapor deposition(PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapordeposition (PECVD), metal organic chemical vapor deposition (MOCVD), ormolecular beam epitaxy (MBE).

8. Additional Alternative Examples

A number of examples have been described. Nevertheless, it will beunderstood that various modifications may be made without departing fromthe spirit and scope of the invention. For example, the recordable layer110 and its sub-layers can have materials and thicknesses different fromthose described above. The recordable layers can be made using methodsother than those described above. In FIG. 10, rather than covering theentire chip area with the recordable layer 110, an additional photo maskcan be used to pattern the recordable layer 110 so that the layer 110only covers the REME area 272, or portions of the REME area 272. In FIG.18, the memory device 400 can include three or more layers that aresimilar to the layers 402 and 404. In FIG. 2A, the metal materialfilling the openings 156 of the recordable layer 110 does not have to bethe same as the upper and lower electrodes 154 and 152. For example,after the recordable layer 110 is formed above the lower electrode 152,a first metal is be deposited to fill the openings 156, and a secondmetal is deposited to form the upper electrode 154.

The memory device can be a memory card having interface and/or physicaldimensions that comply with various storage standards, such as flashmemory standards. The memory device can also have an arbitrary shape.The memory device does not necessarily have to be flat, and can, forexample, conform to the surface contour of a cube, a ball, or any otherarbitrary volume. The memory controller can have differentconfigurations so that the processes for writing and reading data aredifferent from those described above. The recordable electrical memorydevice can be integrated into systems other than those described above.

The alignment shifting technique shown in FIGS. 5A to 5E and 7A to 7Fcan be modified in various ways, e.g., by changing the number ofdifferent positions in which the photo mask 190 is shifted and thedirections of shifts. Memory cells each having, e.g., 3, 5, 6, 7, 8, 10,or more sub-cells can be fabricated. For example, the memory cell shownin FIG. 7D includes 6 sub-cells.

The recordable electrical memory device can be written using, forexample, magnetic or optical methods, and read electronically. Forexample, instead of applying electrical pulses to selected memory cellsto write marks in the cells, a light beam may be used to apply energy toselected memory cells to write the marks. After the marks have beenwritten, an electric read signal is applied to memory cells to detectcontrast in electrical properties, such as resistance, to readinformation stored in the memory cells. The read and write voltages canbe positive or negative.

Other implementations are within the scope of the following claims.

1. A method comprising: fabricating a memory cell of a memory device,comprising forming a first electrode on a substrate; positioning a photomask at a first position relative to the substrate; forming a firstmaterial layer on the first electrode based on a pattern on the photomask; positioning the photo mask at a second position relative to thesubstrate; forming a second material layer above the first materiallayer based on the pattern on the photo mask, the second material layerbeing offset from the first material layer so that a first sub-cell ofthe memory cell includes the first material layer and not the secondmaterial layer, and a second sub-cell of the memory cell includes boththe first and second material layers; and forming a second electrodeabove the first and second material layers and overlapping the firstelectrode.
 2. The method of claim 1 comprising positioning the photomask at a third position and forming a third material layer above thefirst and second material layers based on the pattern on the photo mask,the third material layer being between the first electrode and thesecond electrode, the third material layer being offset from the firstand second material layers so that the memory cell comprises at leastthe first sub-cell, the second sub-cell, and a third sub-cell.
 3. Themethod of claim 2 wherein the third sub-cell includes the first andthird material layers but not the second material layer.
 4. The methodof claim 2 comprising forming a fourth sub-cell that includes the first,second, and third material layers.
 5. The method of claim 2 comprisingpositioning the photo mask at a fourth position and forming a fourthmaterial layer above the first, second, and third material layers basedon the pattern on the photo mask, the fourth layer being between thefirst electrode and the second electrode, the fourth material layerbeing offset from the first, second, and third material layers so thatthe memory cell comprises at least the first sub-cell, the secondsub-cell, the third sub-cell, and a fourth sub-cell.
 6. The method ofclaim 5 comprising positioning the photo mask at a fifth position andforming a fifth material layer above the first, second, third, andfourth material layers based on the pattern on the photo mask, the fifthmaterial layer being offset from the first, second, third, and fourthmaterial layers so that the memory cell comprises at least the firstsub-cell, the second sub-cell, the third sub-cell, the fourth sub-cell,and a fifth sub-cell.
 7. The method of claim 1 wherein positioning thephoto mask at the second position comprises shifting the photo mask fora distance from the first position to the second position in which thedistance is less than a smallest line width of the photo mask.
 8. Themethod of claim 1 wherein forming the first layer comprises forming alayer of material having openings, the openings to allow portions of thefirst electrode to electrically contact portions of the secondelectrode.
 9. The method of claim 1 wherein forming the first materiallayer comprises forming a semiconductor layer or a dielectric layer. 10.The method of claim 1 comprising forming circuitry for applying a writesignal to the memory cell.
 11. The method of claim 1 comprising formingcircuitry for outputting a read signal from the memory cell.
 12. Amethod comprising: fabricating a memory device having memory cells, eachmemory cell having at least two sub-cells, comprising positioning aphoto mask at two or more positions, the photo mask having apredetermined pattern, and for each position of the photo mask, formingat least one material layer based on the predetermined pattern of thephoto mask to cause different sub-cells to have different materiallayers or different combinations of material layers.
 13. The method ofclaim 12 wherein fabricating the sub-cells comprises positioning thephoto mask at three positions to form four sub-cells.
 14. The method ofclaim 12 wherein fabricating the sub-cells comprises positioning thephoto mask at five positions to form nine sub-cells.
 15. The method ofclaim 12 wherein each material layer has a portion that overlaps aportion of another material layer.
 16. The method of claim 12 whereinfabricating the sub-cells comprises depositing a first layer on a lowerelectrode, adjusting an alignment of the photo mask, and depositing asecond layer on the first layer, wherein a first sub-cell includes thefirst layer and not the second layer, and a second sub-cell includesboth the first and second layers.
 17. The method of claim 12 whereinfabricating the sub-cells comprises depositing a first layer on a lowerelectrode, etching the first layer, adjusting an alignment of the photomask, depositing a second layer on the first layer and an exposedportion of the lower electrode, and etching the second layer, wherein afirst sub-cell includes the second layer and not the first layer, and asecond sub-cell includes both the first and second layers.
 18. Themethod of claim 12 wherein positioning the photo mask at two or morepositions comprises positioning the photo mask a first position and asecond position spaced apart from the first position by a distance thatis less than a smallest line width of the photo mask.
 19. The method ofclaim 12 wherein forming at least one material layer for each positionof the photo mask comprises forming a layer of material having openings,the openings to allow portions of the first electrode to electricallycontact portions of the second electrode.
 20. The method of claim 12wherein forming at least one material layer comprises forming at leastone semiconductor or dielectric layer.
 21. A method comprising:fabricating an electronic device on a substrate using a photolithographyprocess, including defining boundaries of components of the electronicdevice by positioning a photo mask at a position relative to thesubstrate, and shifting an alignment of the photo mask according to asequence of steps when defining boundaries of different components, inwhich the smallest distance of shift during the sequence of steps issmaller than a smallest line width of the electronic device.
 22. Themethod of claim 21, comprising forming layers of materials as the photomask is shifted according to the sequence of steps to form materiallayers that are offset from one another to form components havingdifferent layers or different combinations of layers.
 23. An apparatuscomprising: a lithography system comprising a wafer stage to support awafer, a photo mask stage to support a photo mask, at least one steppermotor to drive the photo mask stage, a programmable controller tocontrol the at least one stepper motor to move the photo mask stageaccording to a sequence of steps to fabricate sub-cells of memory cellson the wafer, each of some of the steps involving a movement of thephoto mask stage for a distance less than the smallest line width of thephoto mask such that the sub-cells have dimensions smaller than thesmallest line width of the photo mask, and a storage storinginstructions that when executed cause the programmable controller tocontrol the at least one stepper motor to move the photo mask stageaccording to the sequence of steps to fabricate memory cells each havinga plurality of sub-cells.
 24. The apparatus of claim 23 wherein theinstructions when executed cause the programmable controller to controlthe at least one stepper motor to move the photo mask stage to positionthe photo mask at various locations to cause a first material layer tobe formed at a position that is offset a distance relative to a positionof a second material layer, forming a first sub-cell that includes thefirst material layer but not the second material layer, and a secondsub-cell that includes both the first and second material layers, theoffset distance being less than the smallest line width of the photomask.
 25. An apparatus comprising: means for defining boundaries ofsub-cells of memory cells of a memory device by positioning a photo maskat a position relative to a substrate on which the memory device isfabricated, and means for shifting alignment of the photo mask accordingto a sequence of steps in which the smallest distance of shift duringthe sequence of steps is smaller than a smallest width of the memorycell.